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? 2005 microchip technology inc. ds11177d-page 1 mcp606/7/8/9 features ? low input offset voltage: 250 v (max.) ? rail-to-rail output ? low input bias current: 80 pa (max. at 85c) ? low quiescent current: 25 a (max.) ? power supply voltage: 2.5v to 5.5v ? unity-gain stable ? chip select (cs ) capability: mcp608 ? industrial temperature range: -40c to +85c ? no phase reversal ? available in single, dual and quad packages typical applications ? battery power instruments ? high-impedance applications - photodiode amplifier - ph probe buffer amplifier - infrared detectors - precision integrators - charge amplifier for piezoelectric transducers ? strain gauges ? medical instruments ? test equipment available tools ? spice macro models (at www.microchip.com) ?filterlab ? software (at www.microchip.com) typical application description the mcp606/7/8/9 family of operational amplifiers (op amps) from microchip technology inc. are unity-gain stable with low offset voltage (250 v, max.). performance characteristics include rail-to-rail output swing capability and low input bias current (80 pa at +85c, max.). these features make this family of op amps well suited for single-supply, precision, high- impedance, battery-powered applications. the single mcp606 is available in standard 8-lead pdip, soic and tssop packages, as well as in a sot-23-5 package. the single mcp608 with chip select (cs ) is offered in standard 8-lead pdip, soic and tssop packages. the dual mcp607 is offered in standard 8-lead pdip, soic and tssop packages. finally, the quad mcp609 is offered in standard 14-lead pdip, soic and tssop packages. all devices are fully specified from -40c to +85c, with power supplies from 2.5v to 5.5v. package types low-side battery current sensor r f to load 2.5v r g mcp606 5k 50 k to load v out r sen 10 (v lm ) (v lp ) i l to 5.5v v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc mcp606 pdip, soic,tssop mcp607 pdip, soic,tssop mcp608 pdip, soic,tssop mcp609 pdip, soic,tssop mcp606 sot-23-5 v in + v ss v in ? 1 2 3 5 4 v dd v out v ina + v ina ? v ss v outb v inb ? 1 2 3 4 8 7 6 5 v inb + v dd v outa v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc cs nc v ina + v ina ? v dd v ind ? v ind + 1 2 3 4 14 13 12 11 v ss v outd v outa v inb ? v inb + v outb v inc + v inc ? 5 6 7 10 9 8 v outc 2.5v to 5.5v microp ower cmos op amps
mcp606/7/8/9 ds11177d-page 2 ? 2005 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ?v ss .......................................................................7.0v all inputs and outputs ................... v ss ? 0.3v to v dd +0.3v difference input voltage ...................................... |v dd ?v ss | output short circuit current ..................................continuous current at input pins ....................................................2 ma current at output and supply pins ............................30 ma storage temperature ....................................-65c to +150c maximum junction temperature (t j ) ......................... +150c esd protection on all pins (hbm;mm) ...................2 kv; 200v ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a = +25c, v cm =v dd /2, v out v dd /2 and r l = 100 k to v dd /2. parameters sym min typ max units conditions input offset input offset voltage v os -250 ? +250 v input offset drift with temperature v os / t a ?1.8?v/ct a = -40c to +85c power supply rejection ratio psrr 80 93 ? db input bias current and impedance input bias current i b ?1?pa at temperature i b ??80pat a = +85c input offset bias current i os ?1?pa common mode input impedance z cm ?10 13 ||6 ? ||pf differential input impedance z diff ?10 13 ||6 ? ||pf common mode common mode input range v cmr v ss ?0.3 v dd ? 1.1 v cmrr 75 db common mode rejection ratio cmrr 75 91 ? db v dd = 5v, v cm = -0.3v to 3.9v open-loop gain dc open-loop gain (large-signal) a ol 105 121 ? db r l = 25 k to v dd /2, v out = 50 mv to v dd ?50mv dc open-loop gain (large-signal) a ol 100 118 ? db r l = 5 k to v dd /2, v out = 0.1v to v dd ?0.1v output maximum output voltage swing v ol , v oh v ss +15 ? v dd ?20 mv r l = 25 k to v dd /2, 0.5v output overdrive v ol , v oh v ss +45 ? v dd ?60 mv r l = 5 k to v dd /2, 0.5v output overdrive linear output voltage range v out v ss +50 ? v dd ?50 mv r l = 25 k to v dd /2, a ol 105 db v out v ss + 100 ? v dd ? 100 mv r l = 5 k to v dd /2, a ol 100 db output short circuit current i sc ?7?mav dd = 2.5v i sc ?17?mav dd = 5.5v power supply supply voltage v dd 2.5 ? 5.5 v quiescent current per amplifier i q ? 18.7 25 a i o = 0
? 2005 microchip technology inc. ds11177d-page 3 mcp606/7/8/9 figure 1-1: timing diagram for the cs pin on the mcp608. ac characteristics electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out v dd /2, r l = 100 k to v dd /2 and c l =60pf. parameters sym min typ max units conditions ac response gain bandwidth product gbwp ? 155 ? khz phase margin pm ? 62 ? g = +1 slew rate sr ? 0.08 ? v/s g = 1 noise input noise voltage e ni ?2.8?v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?38?nv/ hz f = 1 khz input noise current density i ni ?3?fa/ hz f = 1 khz mcp608 chip select (cs ) characteristics electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a = 25c, v cm =v dd /2, v out v dd /2, r l = 100 k to v dd /2 and c l =60pf. parameters sym min typ max units conditions cs low specifications cs logic threshold, low v il v ss ?0.2v dd v cs input current, low i csl -0.1 0.01 ? a cs = 0.2v dd cs high specifications cs logic threshold, high v ih 0.8 v dd ?v dd v cs input current, high i csh ? 0.01 0.1 a cs = v dd cs input high, gnd current i ss -2 -0.05 ? a cs = v dd amplifier output leakage, cs high i o(leak) ?10 ?nacs = v dd cs dynamic specifications cs low to amplifier output turn-on time t on ? 9 100 s cs = 0.2v dd to v out = 0.9(v dd /2), g = +1 v/v, r l = 1 k to v ss cs high to amplifier output hi-z t off ?0.1? scs = 0.8v dd to v out = 0.1(v dd /2), g = +1 v/v, r l = 1 k to v ss cs hysteresis v hyst ?0.6? vv dd = 5.0v cs v out i ss i cs v il v ih t on t off -50 na (typ.) -50 na (typ.) -18.7 a (typ.) -50 na (typ.) -50 na (typ.) hi-z hi-z
mcp606/7/8/9 ds11177d-page 4 ? 2005 microchip technology inc. temperature characteristics electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v and v ss =gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +85 c operating temperature range t a -40 ? +125 c note 1 storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot23 ja ? 256 ? c/w thermal resistance, 8l-pdip ja ?85?c/w thermal resistance, 8l-soic ja ? 163 ? c/w thermal resistance, 8l-tssop ja ? 124 ? c/w thermal resistance, 14l-pdip ja ?70?c/w thermal resistance, 14l-soic ja ? 120 ? c/w thermal resistance, 14l-tssop ja ? 100 ? c/w note 1: the mcp606/7/8/9 operate over this extended temperature range, but with r educed performance. in any case, the junction temperature (t j ) must not exceed the absolute maximum specification of +150c.
? 2005 microchip technology inc. ds11177d-page 5 mcp606/7/8/9 2.0 typical performance curves note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =25c, v cm =v dd /2, v out v dd /2, r l =100k to v dd /2 and c l =60pf. figure 2-1: input offset voltage at v dd =5.5v. figure 2-2: input offset voltage at v dd =2.5v. figure 2-3: quiescent current vs. power supply voltage. figure 2-4: input offset voltage drift magnitude at v dd =5.5v. figure 2-5: input offset voltage drift magnitude at v dd =2.5v. figure 2-6: quiescent current vs. ambient temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% -250 -200 -150 -100 -50 0 50 100 150 200 250 input offset voltage (v) percentage of occurances 1200 samples v dd = 5.5v 0% 2% 4% 6% 8% 10% 12% 14% 16% -250 -200 -150 -100 -50 0 50 100 150 200 250 input offset voltage (v) percentage of occurances 1200 samples v dd = 2.5v 0 2 4 6 8 10 12 14 16 18 20 22 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) quiescent current per amplifier (a) t a = +85c t a = +25c t a = -40c 0% 5% 10% 15% 20% 25% 0 1 2 3 4 5 6 7 8 9 10 input offset voltage drift magnitude (v/c) percentage of occurances 1200 samples v dd = 5.5v 0% 5% 10% 15% 20% 25% 0 1 2 3 4 5 6 7 8 9 10 input offset voltage drift magnitude (v/c) percentage of occurances 1200 samples v dd = 2.5v 12 14 16 18 20 22 24 -50-25 0 255075100 ambient temperature (c) quiescent current per amplifier (a) v dd = 5.5v v dd = 2.5v
mcp606/7/8/9 ds11177d-page 6 ? 2005 microchip technology inc. note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =25c, v cm =v dd /2, v out v dd /2, r l =100k to v dd /2 and c l =60pf. figure 2-7: input offset voltage vs. ambient temperature. figure 2-8: open-loop gain and phase vs. frequency. figure 2-9: channel-to-channel separation (mcp607 and mcp609 only). figure 2-10: input offset voltage vs. common mode input voltage. figure 2-11: gain bandwidth product, phase margin vs. ambient temperature. figure 2-12: input noise voltage density vs. frequency. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 ambient temperature (c) input offset voltage (v) v dd =2.5v v dd = 5.5v representative part -20 0 20 40 60 80 100 120 frequency (hz) open-loop gain (db) -225 -180 -135 -90 -45 0 45 90 open-loop phase () gain phase r l = 25 k 0.01 1 0.1 10 1k 100 10k 1m 100k 80 90 100 110 120 130 140 1.e+02 1.e+03 1.e+04 1.e+0 5 frequency (hz) channel-to-channel separation (db) referred to input 100 100k 10k 1k -20 0 20 40 60 80 100 120 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common mode input voltage (v) input offset voltage (v) t a = +85c t a = +25c t a = -40c v dd = 5.5v 0 20 40 60 80 100 120 140 160 -50 -25 0 25 50 75 100 ambient temperature (c) gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 phase margin () phase margin gbwp v dd = 5.0v 10 100 1000 1.e- 01 1.e+0 0 1.e+0 1 1.e+0 2 1.e+0 3 1.e+0 4 1.e+0 5 frequency (hz) input noise voltage density (nv/ ? hz) 0.1 1 10 100 1k 10k 100k
? 2005 microchip technology inc. ds11177d-page 7 mcp606/7/8/9 note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =25c, v cm =v dd /2, v out v dd /2, r l =100k to v dd /2 and c l =60pf. figure 2-13: input bias current, input offset current vs. ambient temperature. figure 2-14: dc open-loop gain vs. load resistance. figure 2-15: cmrr, psrr vs. frequency. figure 2-16: input bias current, input offset current vs. common mode input voltage. figure 2-17: dc open-loop gain vs. power supply voltage. figure 2-18: cmrr, psrr vs. ambient temperature. 0.1 1 10 100 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) input bias and offset currents (pa) i b | i os | v dd = 5.5v v cm = v dd 100 105 110 115 120 125 130 135 1.e+02 1.e+03 1.e+04 1.e+0 5 load resistance ( ) dc open-loop gain (db) v dd = 2.5v v dd = 5.5v 100 100k 10k 1k 0 20 40 60 80 100 120 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 frequency (hz) cmrr and psrr (db) psrr- psrr+ cmrr 0.1 1 10 100 1k 10k -10 0 10 20 30 40 50 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias and offset currents (pa) i b i os t a = +85c v dd = 5.5v 90 100 110 120 130 140 150 0.00.51.01.52.02.53.03.54.04.55.05.5 power supply voltage (v) dc open-loop gain (db) r l = 25 k 75 80 85 90 95 100 -50-25 0 255075100 ambient temperature (c) cmrr and psrr (db) cmrr psrr
mcp606/7/8/9 ds11177d-page 8 ? 2005 microchip technology inc. note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =25c, v cm =v dd /2, v out v dd /2, r l =100k to v dd /2 and c l =60pf. figure 2-19: output voltage headroom vs. output current magnitude. figure 2-20: maximum output voltage swing vs. frequency. figure 2-21: slew rate vs. ambient temperature. figure 2-22: output voltage headroom vs. ambient temperature at r l =5k . figure 2-23: the mcp606/7/8/9 show no phase reversal. figure 2-24: output short circuit current magnitude vs. ambient temperature. 1 10 100 1000 0.1 1 10 100 output current (ma) output voltage headroom; v dd ? v oh and v ol ? v ss (mv) v dd - v oh , v dd = 2.5v v ol - v ss , v dd = 2.5v v dd - v oh , v dd = 5.5v v ol - v ss , v dd = 5.5v 0.1 1 10 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) maximum output voltage swing (v) v dd = 2.5v 100 100k 10k 1k v dd = 5.5v 0.00 0.02 0.04 0.06 0.08 0.10 0.12 -50 -25 0 25 50 75 100 ambient temperature (c) slew rate (v/s) low to high high to low 0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 ambient temperature (c) output voltage headroom; v dd ? v oh and v ss ? v ol (mv) v dd ? v oh , v dd = 5.5v v ol ? v ss , v dd = 5.5v r l = 5 k v dd ? v oh , v dd = 2.5v v ol ? v ss , v dd = 2.5v -1 0 1 2 3 4 5 6 time (100 s/div) input and output voltages (v) v out v in g = +2 v/v v dd = 5.0v 0 5 10 15 20 25 -50 -25 0 25 50 75 100 ambient temperature (c) output short circuit current magnitude (ma) +i sc , v dd = 2.5v | -i sc |, v dd = 2.5v +i sc , v dd = 5.5v | -i sc |, v dd = 5.5v
? 2005 microchip technology inc. ds11177d-page 9 mcp606/7/8/9 note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =25c, v cm =v dd /2, v out v dd /2, r l =100k to v dd /2 and c l =60pf. figure 2-25: large-signal, non-inverting pulse response. figure 2-26: small-signal, non-inverting pulse response. figure 2-27: chip select (cs ) hysteresis (mcp608 only). figure 2-28: large-signal, inverting pulse response. figure 2-29: small-signal, inverting pulse response. figure 2-30: amplifier output response times vs. chip select (cs ) pulse (mcp608 only). 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (50 s/div) output voltge (v) v dd = 5.0v time (50 s/div) output voltage (20 mv/div) v dd = 5.0v -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 cs input voltage (v) internal cs switch output (v) amplifier output active amplifier output hi-z v dd = 5.0v hysteresis cs input high to low cs input low to high 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (50 s/div) output voltage (v) v dd = 5.0v time (50 s/div) output voltage (20 mv/div) r l = 25 k 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (5 s/div) output voltage (v) -35 -30 -25 -20 -15 -10 -5 0 5 10 15 chip select voltage (v) cs v out output hi-z output hi-z output enabled g = +1 v/v r l = 1 k to v ss
mcp606/7/8/9 ds11177d-page 10 ? 2005 microchip technology inc. 3.0 pin descriptions descriptions of the pins are listed in table 3-1. table 3-1: pin function table. 3.1 analog outputs the output pins are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high- impedance cmos inputs with low bias currents. 3.3 power supply (v ss and v dd ) the positive power supply pin (v dd ) is 2.5v to 5.5v higher than the negative power supply pin (v ss ). for normal operation, the output pins are at voltages between v ss and v dd ; while the input pins are at voltages between v ss ? 0.3v and v dd +0.3v. typically, these parts are used in a single-supply (positive) configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1 f) within 2 mm of the v dd pin. these parts can share a bulk capacitor with nearby analog parts (typically 1 f or larger) within 100 mm of the v dd pin. 3.4 digital input the chip select (cs ) pin is a schmitt-triggered, cmos logic input. it is used to place the mcp608 op amp in a low-power mode, with the output(s) in a hi-z state. mcp606 (pdip, soic, tssop) mcp606 (sot-23-5) mcp607 mcp608 mcp609 symbol description 61161v out , v outa output (op amp a) 24222v in ?, v ina ? inverting input (op amp a) 33333v in +, v ina + non-inverting input (op amp a) 75474v dd positive power supply ??5?5v inb + non-inverting input (op amp b) ??6?6v inb ? inverting input (op amp b) ??7?7v outb output (op amp b) ????8v outc output (op amp b) ????9v inc ? inverting input (op amp c) ????10v inc + non-inverting input (op amp c) 428411v ss negative power supply ????12v ind + non-inverting input (op amp d) ????13v ind ? inverting input (op amp d) ????14v outd output (op amp d) ???8?cs chip select 1, 5, 8 ? ? 1, 5 ? nc no internal connection
? 2005 microchip technology inc. ds11177d-page 11 mcp606/7/8/9 4.0 applications information the mcp606/7/8/9 family of op amps is manufactured using microchip?s state-of-the-art cmos process these op amps are unity-gain stable and suitable for a wide range of general purpose applications. 4.1 inputs the mcp606/7/8/9 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. figure 2-23 shows the input voltage exceeding the supply voltage without any phase rever- sal. the inputs of the mcp606/7/8/9 op amps connect to a differential pmos input stage. the common mode input voltage range (v cmr ) includes ground in single- supply systems (v ss ), but does not include v dd . this means that the amplifier input behaves linearly as long as the common mode input voltage (v cm ) is kept within the specified v cmr limits (v ss ?0.3v to v dd ?1.1v at +25c). input voltages that exceed the absolute maximum voltage range (v ss ? 0.3v to v dd + 0.3v) can cause excessive current to flow into or out of the input pins. current beyond 2 ma can cause reliability problems. applications that exceed this rating must be externally limited with a resistor, as shown in figure 4-1. figure 4-1: input current-limiting resistor (r in ). 4.2 rail-to-rail output there are two specifications that describe the output- swing capability of the mcp606/7/8/9 family of op amps. the first specification (maximum output voltage swing) defines the absolute maximum swing that can be achieved under the specified load conditions. for instance, the output voltage swings to within 15 mv of the negative rail with a 25 k load to v dd /2. figure 2-23 shows how the output voltage is limited when the input goes beyond the linear region of operation. the second specification that describes the output- swing capability of these amplifiers (linear output voltage range) defines the maximum output swing that can be achieved while the amplifier still operates in its linear region. to verify linear operation in this range, the large-signal dc open-loop gain (a ol ) is measured at points inside the supply rails. the measurement must meet the specified a ol conditions in the specification table. 4.3 capacitive loads driving large capacitive loads can cause stability problems for voltage-feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain-peaking in the frequency response, with overshoot and ringing in the step response. a unity-gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 60 pf when g = +1), a small series resistor at the output (r iso in figure 4-2) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-2: output resistor, r iso stabilizes large capacitive loads. figure 4-3 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n =+2v/v). figure 4-3: recommended r iso values for capacitive loads. r in maximum expected v in () v dd ? 2 ma ------------------------------------------------------------------------------ r in v ss minimum expected v in () ? 2 ma --------------------------------------------------------------------------- v in mcp60x r in v out v in mcp60x r iso v out c l 100 1000 10000 10 100 1000 10000 normalized load capacitance; c l /g n (f) recommended r iso ( : ) 10p 10n 1n 100p 100 10k 1k g n = +1 g n = +2 g n t +4
mcp606/7/8/9 ds11177d-page 12 ? 2005 microchip technology inc. after selecting r iso for your circuit, double-check the resulting frequency response peaking and step response overshoot. modify r iso ?s value until the response is reasonable. bench evaluation and simula- tions with the mcp606/7/8/9 spice macro model are helpful. 4.4 mcp608 chip select (cs ) the mcp608 is a single op amp with chip select (cs ). when cs is pulled high, the supply current drops to 50 na (typ.) and flows through the cs pin to v ss . when this happens, the amplifier output is put into a high- impedance state. by pulling cs low, the amplifier is enabled. if the cs pin is left floating, the amplifier may not operate properly. figure 1-1 shows the output voltage and supply current response to a cs pulse. 4.5 supply bypass with this family of operational amplifiers, the power supply pin (v dd for single-supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high-frequency performance. it also needs a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other nearby analog parts. 4.6 pcb surface leakage in applications where low input bias current is critical, printed circuit board (pcb) surface-leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 . a 5v difference would cause 5 pa of current to flow, which is greater than the mcp606/7/8/9 family?s bias current at 25c (1 pa, typ.). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is shown in figure 4-4. figure 4-4: example guard ring layout for inverting gain. 1. non-inverting gain and unity-gain buffer: a) connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b) connect the guard ring to the inverting input pin (v in ?). this biases the guard ring to the common mode input voltage. 2. inverting gain and transimpedance gain (convert current to voltage, such as photo detectors) amplifiers: a) connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b) connect the inverting pin (v in ?) to the input with a wire that does not touch the pcb surface. 4.7 application circuits 4.7.1 low-side battery current sensor the mcp606/7/8/9 op amps can be used to sense the load current on the low-side of a battery using the circuit in figure 4-5. in this circuit, the current from the power supply (minus the current required to power the mcp606) flows through a sense resistor (r sen ), which converts it to voltage. this is gained by the the amplifier and resistors, r g and r f . since the non-inverting input of the amplifier is at the load?s negative supply (v lm ), the gain from r sen to v out is r f /r g . figure 4-5: low side battery current sensor. since the input bias current and input offset voltage of the mcp606 are low, and the input is capable of swing- ing below ground, there is very little error generated by the amplifier. the quiescent current is very low, which helps conserve battery power. the rail-to-rail output makes it possible to read very low currents. guard ring v ss v in -v in + v out v lm i + l r sen r f r g ? () = r f to load 2.5v r g mcp606 5k 50 k to load v out r sen 10 (v lm ) (v lp ) i l to 5.5v
? 2005 microchip technology inc. ds11177d-page 13 mcp606/7/8/9 4.7.2 photodiode amplifiers sensors that produce an output current and have high output impedance can be connected to a transimped- ance amplifier. the transimpedance amplifier converts the current into voltage. photodiodes are one sensor that produce an output current. the key op amp characteristics that are needed for these circuits are: low input offset voltage, low input bias current, high input impedance and an input common mode range that includes ground. the low input offset voltage and low input bias current support a very low voltage drop across the photodiode; this gives the best photodiode linearity. since the photodiode is biased at ground, the op amp?s input needs to function well both above and below ground. 4.7.2.1 photo-voltaic mode figure 4-6 shows a transimpedance amplifier with a photodiode (d 1 ) biased in the photo-voltaic mode (0v across d 1 ), which is used for precision photodiode sensing. as light impinges on d 1 , charge is generated, causing a current to flow in the reverse bias direction of d 1 . the op amp?s negative feedback forces the voltage across the d 1 to be nearly 0v. resistor r 2 converts the current into voltage. capacitor c 2 limits the bandwidth and helps stabilize the circuit when d 1 ?s junction capacitance is large. figure 4-6: photodiode (in photo-voltaic mode) and transimpedance amplifier. 4.7.2.2 photo-conductive mode figure 4-6 shows a transimpedance amplifier with a photodiode (d 1 ) biased in the photo-conductive mode (d 1 is reverse biased), which is used for high-speed applications. as light impinges on d 1 , charge is generated, causing a current to flow in the reverse bias direction of d 1 . placing a negative bias on d 1 significantly reduces its junction capacitance, which allows the circuit to operate at a much higher speed. this reverse bias also increases the dark current and current noise, however. resistor r 2 converts the current into voltage. capacitor c 2 limits the bandwidth and helps stabilize the circuit when d 1 ?s junction capacitance is large. figure 4-7: photodiode (in photo- conductive mode) and transimpedance amplifier. 4.7.3 two op amp instrumentation amplifier the two op amp instrumentation amplifier shown in figure 4-8 serves the function of taking the difference of two input voltages, level-shifting it and gaining it to the output. this configuration is best suited for higher gains (i.e., gain > 3 v/v). the reference voltage (v ref ) is typically at mid-supply (v dd /2) in a single-supply environment. figure 4-8: two op amp instrumentation amplifier. the key specifications that make the mcp606/7/8/9 family appropriate for this application circuit are low input bias current, low offset voltage and high common- mode rejection. v out i d1 r 2 = r 2 d 1 mcp606 v out light c 2 v dd i d1 v out i d1 r 2 = r 2 d 1 mcp606 v out light c 2 v dd i d1 vb v b 0 < v out v 1 v 2 ? () 1 r 1 r 2 ------ 2r 1 r g --------- - ++ ?? ?? ?? v ref + = r 2 r 1 mcp607 v out v 2 v ref ? r 1 r 2 v 1 r g mcp607 ?
mcp606/7/8/9 ds11177d-page 14 ? 2005 microchip technology inc. 4.7.4 three op amp instrumentation amplifier a classic, three op amp instrumentation amplifier is illustrated in figure 4-9. the two input op amps provide differential signal gain and a common mode gain of +1. the output op amp is a difference amplifier, which converts its input signal from differential to a single ended output; it rejects common mode signals at its input. the gain of this circuit is simply adjusted with one resistor (r g ). the reference voltage (v ref ) is typically referenced to mid-supply (v dd /2) in single-supply applications. figure 4-9: three op amp instrumentation amplifier. 4.7.5 precision gain with good load isolation in figure 4-10, the mcp606 op amps, r 1 and r 2 provide a high gain to the input signal (v in ). the mcp606?s low offset voltage makes this an accurate circuit. the mcp601 is configured as a unity-gain buffer. it isolates the mcp606?s output from the load, increasing the high-gain stage?s precision. since the mcp601 has a higher output current, with the two amplifiers being housed in separate packages, there is minimal change in the mcp606?s offset voltage due to loading effect. figure 4-10: precision gain with good load isolation. v out v 1 v 2 ? () 1 2r 2 r g --------- + ?? ?? ?? r 4 r 3 ------ ?? ?? ?? v ref + = r 2 mcp607 v ref v 1 ? r 4 r 3 mcp606 r 2 r g mcp607 v out v 2 ? r 4 r 3 v out v in 1r 2 r 1 ? + () = r 2 r 1 mcp606 v out v in mcp601
? 2005 microchip technology inc. ds11177d-page 15 mcp606/7/8/9 5.0 design tools microchip provides the basic design tools needed for the mcp606/7/8/9 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp606/7/8/9 op amps is available on our web site at www.microchip.com. this model is intended to be an initial design tool that works well in the op amp?s linear region of operation at room temperature. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software the filterlab software is an innovative tool that simplifies analog active-filter (using op amps) design. it is available free of charge from our web site at www.microchip.com. the filterlab software tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance.
mcp606/7/8/9 ds11177d-page 16 ? 2005 microchip technology inc. 6.0 packaging information 6.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead tssop example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn xxxx yyww nnn 5-lead sot-23-5 example: xxnn sb25 mcp606 i/p^^256 0545 mcp606 sn^^0545 256 606 i545 256 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e
? 2005 microchip technology inc. ds11177d-page 17 mcp606/7/8/9 package marking information (continued) mcp609 0545 i/p^^256 14-lead pdip (300 mil) ( mcp609 )example: 14-lead tssop ( mcp609 ) example: 14-lead soic (150 mil) ( mcp609 ) example: xxxxxxxxxxxxxx xxxxxxxxxxxnnn yyww xxxxxxxxxx yywwnnn xxxxxxxx yyww nnn mcp609 0545256 609ist 0545 256 xxxxxxxxxx 3 e i/sl^^ 3 e
mcp606/7/8/9 ds11177d-page 18 ? 2005 microchip technology inc. 5-lead plastic small outline transistor (ot) (sot23) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 p d b n e e1 l c a2 a a1 p1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-178 drawing no. c04-091 significant characteristic
? 2005 microchip technology inc. ds11177d-page 19 mcp606/7/8/9 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
mcp606/7/8/9 ds11177d-page 20 ? 2005 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2005 microchip technology inc. ds11177d-page 21 mcp606/7/8/9 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c 1 2 d n p b e e1 foot angle 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
mcp606/7/8/9 ds11177d-page 22 ? 2005 microchip technology inc. 14-lead plastic dual in-line (p) ? 300 mil (pdip) e1 n d 1 2 eb e c a a1 b b1 l a2 p units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic
? 2005 microchip technology inc. ds11177d-page 23 mcp606/7/8/9 14-lead plastic small outline (sl) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-065 significant characteristic
mcp606/7/8/9 ds11177d-page 24 ? 2005 microchip technology inc. 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 8 4 0 8 4 0 foot angle 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b1 lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l c 2 1 d n b p e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic
? 2005 microchip technology inc. ds11177d-page 25 mcp606/7/8/9 appendix a: revision history revision d (february 2005) the following is the list of modifications: 1. added section 3.0 ?pin descriptions? . 2. updated section 4.0 ?applications information? . 3. added section 4.3 ?capacitive loads? 4. updated section 5.0 ?design tools? to include filterlab ? and to point to the latest spice macro model. 5. corrected and updated section 6.0 ?packaging information? . 6. added section appendix a: ?revision history? . revision c (january 2001) revision b (may 2000) revision a (january 2000) ? original release of this document.
mcp606/7/8/9 ds11177d-page 26 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds11177d-page 27 mcp606/7/8/9 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device mcp606 = single op amp mcp606t = single op amp tape and reel (soic, tssop) mcp607 = dual op amp mcp607t = dual op amp tape and reel (soic, tssop) mcp608 = single op amp with cs mcp608t = single op amp with cs tape and reel (soic, tssop) mcp609 = quad op amp mcp609t = quad op amp tape and reel (soic, tssop) temperature range i = -40 c to +85 c package ot = plastic sot-23, 5-lead p = plastic dip (300 mil body), 8-lead & 14-lead sn = plastic soic (150 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead st = plastic tssop, 8-lead & 14-lead part no. x /xx package temperature range device examples: a) mcp606-i/p: industrial temperature, 8ld pdip package. b) mcp606-i/sn: industrial temperature, 8ld soic package. c) mcp606t-i/sn: tape and reel, industrial temperature, 8ld soic package. d) mcp606-i/st: industrial temperature, 8ld tssop package. e) mcp606-i/ot: industrial temperature, 5ld sot-23 package. f) mcp606t-i/ot: tape and reel, industrial temperature, 5ld sot-23 package. a) mcp607-i/p: industrial temperature, 8ld pdip package. b) mcp607t-i/p: industrial temperature, 8ld pdip package. a) mcp608-i/sn: industrial temperature, 8ld soic package. b) mcp608t-i/sn: tape and reel, industrial temperature, 8ld soic package. a) mcp609-i/p: industrial temperature, 14ld pdip package. b) mcp609t-i/p: industrial temperature, 14ld pdip package.
mcp606/7/8/9 ds11177d-page 28 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds11177d-page 29 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance and wiperlock are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned her ein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds11177d-page 30 ? 2005 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta alpharetta, ga tel: 770-640-0034 fax: 770-640-0307 boston westford, ma tel: 978-692-3848 fax: 978-692-3821 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 san jose mountain view, ca tel: 650-215-1444 fax: 650-961-0286 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8676-6200 fax: 86-28-8676-6599 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - qingdao tel: 86-532-502-7355 fax: 86-532-502-7205 asia/pacific india - bangalore tel: 91-80-2229-0061 fax: 91-80-2229-0062 india - new delhi tel: 91-11-5160-8631 fax: 91-11-5160-8632 japan - kanagawa tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 taiwan - hsinchu tel: 886-3-572-9526 fax: 886-3-572-6459 europe austria - weis tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark - ballerup tel: 45-4450-2828 fax: 45-4485-2829 france - massy tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - ismaning tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 england - berkshire tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 10/20/04

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